1. Field of the Invention
The present invention relates to a non-volatile memory cell, and more particularly, to a non-volatile memory cell with enhanced endurance.
2. Description of the Prior Art
Non-volatile memory is a kind of memory which is capable of storing data without power supply. Common non-volatile memories include magnetic memory devices, CD-ROM, flash memory, etc. In general, the non-volatile memory is fabricated by a logic based complementary metal oxide semiconductor (CMOS) process. Each non-volatile memory cell of the non-volatile memory may operate in a read mode, a program mode and an erase mode.
The non-volatile memory cells in the prior art suffer from the poor endurance. Specifically, when the non-volatile memory cell operates in a program/erase mode, a tunneling effect is produced on a floating gate of the non-volatile memory cell by apply proper bias voltages to perform a program/erase operation. After the program/erase operation of the non-volatile memory cells in the prior art is performed many times, a threshold voltage of a transistor of the non-volatile memory cell raises due to the tunneling effect, and the transistor of the non-volatile memory cell degrades, such that the read performance of the non-volatile memory cell is reduced.
For example, FIG. 1A is a top view of a circuit layout of a non-volatile memory cell 10 according to U.S. Pat. No. 8,625,350, and FIG. 1B is a schematic circuit diagram of the non-volatile memory cell 10. The non-volatile memory cell 10 comprises a coupling device 100, a read transistor 110, an erase transistor 120, a word transistor 130 and a bit transistor 140. When the non-volatile memory cell 10 operates in an erase mode, the erase transistor 120 generates the tunneling effect, and the electrons are ejected from a floating gate FG1 of the read transistor 110. When the non-volatile memory cell 10 operates in a program mode, the read transistor 110 generates the tunneling effect to inject the electrons to the floating gate FG1. When the non-volatile memory cell 10 operates in a read mode, a logic status of the non-volatile memory cell 10 is determined according to a read current IR1 flowing through the read transistor 110. Notably, the electrons are injected into the floating gate FG1 in the program mode, causing the charge trapping effect in the read transistor 110. After the program operation is performed many times, the read transistor 110 is gradually degraded, i.e., the threshold voltage of the read transistor 110 is gradually increased. Thus, determination of the read current IR1 of the non-volatile memory cell 10 in the read mode would be affected, and the read performance of the non-volatile memory cell 10 is reduced.
In another perspective, FIG. 2A is a top view of a circuit layout of a non-volatile memory cell 20 according to U.S. Pat. No. 7,326,994, and FIG. 2B is a schematic circuit diagram of the non-volatile memory cell 20. The non-volatile memory cell 20 comprises a coupling device 200, a read transistor 210, a select transistor 230 and an erase transistor 220. When the non-volatile memory cell 20 needs to eject the electrons from a floating gate FG2, the tunneling effect is produced on the erase transistor 220, and the electrons are ejected from the floating gate FG2. When the non-volatile memory cell 20 needs to inject the electrons into the floating gate FG2, the tunneling injection is produced on the read transistor 210 to inject the electrons into the floating gate FG2. When the non-volatile memory cell 20 operates in the read mode, a logic status of the non-volatile memory cell 20 is determined according to a read current IR2 flowing through the read transistor 210. Similarly, the electrons are injected into the floating gate FG2, causing the charge trapping effect in the read transistor 210. After the tunneling injection is performed many times, the read transistor 210 is gradually degraded, i.e., the threshold voltage of the read transistor 210 is gradually increased. Thus, determination of the read current I21 of the non-volatile memory cell 20 in the read mode would be affected, and the read performance of the non-volatile memory cell 20 is reduced.
Therefore, how to avoid the read performance of the non-volatile memory cell being affected by the degradation of the transistor and enhance the endurance of the non-volatile memory cell is a significant objective in the field.